MA180025 Microchip Technology, MA180025 Datasheet - Page 133

• Manufacturer Part Number: MA180025
• Description: MODULE PLUG-IN PIC18F87J90 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180025

• Accessory Type: Plug-In Module (PIM) - PIC18F87J90
• Product: Microcontroller Modules
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PICDEM LCD 2 Demonstration Board (DM163030)
• For Use With: DM163030 - KIT DEV PICDEM LCD2
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.8
PORTG is a 5-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISG and LATG. All pins on PORTG are digital only
and tolerate voltages up to 5.5V.
PORTG is multiplexed with both AUSART and LCD
functions (Table 10-16). When operating as I/O, all
PORTG pins have Schmitt Trigger input buffers. The
RG1 pin is also configurable for open-drain output
when the AUSART is active. Open-drain configuration
is selected by setting the U2OD control bit (LATG<7>).
RG4 is multiplexed with LCD segment drives controlled
by bits in the LCDSE2 register and as the RTCC pin.
The I/O port function is only available when the
segments are disabled.
RG3 and RG2 are multiplexed with the V
the LCD charge pump and RG0 is multiplexed with the
LCDBIAS0 bias voltage input. When these pins are
used for LCD bias generation, the I/O and other
functions are unavailable.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS bit
settings. The pin override value is not loaded into the
TRIS register. This allows read-modify-write of the TRIS
register without concern due to peripheral overrides.
 2010 Microchip Technology Inc.
PORTG, TRISG and
LATG Registers
LCAP
pins for
PIC18F87J90 FAMILY
Although the port itself is only five bits wide, the
PORTG<7:5> bits are still implemented to control the
weak pull-ups on the I/O ports associated with PORTD,
PORTE and PORTJ. Clearing these bits enables the
respective port pull-ups. All pull-ups are disabled by
default on all device Resets.
Most of the corresponding TRISG and LATG bits are
implemented as open-drain control bits for CCP1,
CCP2 and SPI (TRISG<7:5>), and the USARTs
(LATG<7:6>). Setting these bits configures the output
pin for the corresponding peripheral for open-drain
operation. LATG<5> is not implemented.
EXAMPLE 10-7:
CLRF
CLRF
MOVLW
MOVWF
PORTG
LATG
04h
TRISG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
INITIALIZING PORTG
DS39933D-page 133