MA180025 Microchip Technology, MA180025 Datasheet - Page 141

• Manufacturer Part Number: MA180025
• Description: MODULE PLUG-IN PIC18F87J90 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180025

• Accessory Type: Plug-In Module (PIM) - PIC18F87J90
• Product: Microcontroller Modules
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PICDEM LCD 2 Demonstration Board (DM163030)
• For Use With: DM163030 - KIT DEV PICDEM LCD2
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.3
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS<2:0> bits
(T0CON<3:0>)
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-2 increments, are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
TABLE 11-1:
 2010 Microchip Technology Inc.
TMR0L
TMR0H
INTCON
T0CON
TRISA
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.
Note 1:
Note:
Name
Prescaler
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Timer0 Register Low Byte
Timer0 Register High Byte
GIE/GIEH PEIE/GIEL TMR0IE
TRISA7
TMR0ON
Bit 7
which
REGISTERS ASSOCIATED WITH TIMER0
(1)
determine
TRISA6
T08BIT
Bit 6
(1)
the
TRISA5
T0CS
Bit 5
prescaler
TRISA4
INT0IE
T0SE
Bit 4
PIC18F87J90 FAMILY
TRISA3
11.3.1
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before
re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
RBIE
Bit 3
PSA
Timer0 Interrupt
TMR0IF
TRISA2
T0PS2
SWITCHING PRESCALER
ASSIGNMENT
Bit 2
TRISA1
INT0IF
T0PS1
Bit 1
TRISA0
T0PS0
RBIF
Bit 0
DS39933D-page 141
on page
Values
Reset
60
60
59
60
62