MA180025 Microchip Technology, MA180025 Datasheet - Page 352

MODULE PLUG-IN PIC18F87J90 PIM

MA180025

Manufacturer Part Number
MA180025
Description
MODULE PLUG-IN PIC18F87J90 PIM
Manufacturer
Microchip Technology
Series
PIC®r
Datasheets

Specifications of MA180025

Accessory Type
Plug-In Module (PIM) - PIC18F87J90
Product
Microcontroller Modules
Silicon Manufacturer
Microchip
Core Architecture
PIC
Core Sub-architecture
PIC18
Silicon Core Number
PIC18F
Silicon Family Name
PIC18FxxJxx
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
PICDEM LCD 2 Demonstration Board (DM163030)
For Use With
DM163030 - KIT DEV PICDEM LCD2
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MA180025
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
MA180025
Manufacturer:
MICROCHIP
Quantity:
12 000
PIC18F87J90 FAMILY
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39933D-page 352
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
No
No
No
Q1
Q1
Q1
PC
PC
Bit Test File, Skip if Clear
BTFSC f, b {,a}
0  f  255
0  b  7
a [0,1]
skip if (f<b>) = 0
None
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
register ‘f’
HERE
FALSE
TRUE
operation
operation
operation
Read
1011
No
No
No
=
=
=
=
=
Q2
Q2
Q2
by a 2-word instruction.
address (HERE)
0;
address (TRUE)
1;
address (FALSE)
BTFSC
:
:
bbba
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
FLAG, 1, 0
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
No
No
No
Q1
Q1
Q1
PC
PC
Bit Test File, Skip if Set
BTFSS f, b {,a}
0  f  255
0  b < 7
a [0,1]
skip if (f<b>) = 1
None
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
register ‘f’
HERE
FALSE
TRUE
operation
operation
operation
Read
1010
No
No
No
=
=
=
=
=
Q2
Q2
Q2
 2010 Microchip Technology Inc.
address (HERE)
0;
address (FALSE)
1;
address (TRUE)
3 cycles if skip and followed
by a 2-word instruction.
BTFSS
:
:
bbba
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
FLAG, 1, 0
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff

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