MA180025 Microchip Technology, MA180025 Datasheet - Page 315

• Manufacturer Part Number: MA180025
• Description: MODULE PLUG-IN PIC18F87J90 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180025

• Accessory Type: Plug-In Module (PIM) - PIC18F87J90
• Product: Microcontroller Modules
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PICDEM LCD 2 Demonstration Board (DM163030)
• For Use With: DM163030 - KIT DEV PICDEM LCD2
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.3.2
There is a small amount of capacitance from the inter-
nal A/D Converter sample capacitor as well as stray
capacitance from the circuit board traces and pads that
affect the precision of capacitance measurements. A
measurement of the stray capacitance can be taken by
making sure the desired capacitance to be measured
has been removed. The measurement is then
performed using the following steps:
1.
2.
3.
4.
5.
6.
where I is known from the current source measurement
step, t is a fixed delay and V is measured by performing
an A/D conversion.
 2010 Microchip Technology Inc.
Initialize the A/D Converter and the CTMU.
Set EDG1STAT (= 1).
Wait for a fixed delay of time, t.
Clear EDG1STAT.
Perform an A/D conversion.
Calculate the stray and A/D sample capacitances:
C
OFFSET
CAPACITANCE CALIBRATION
= C
STRAY
+ C
AD
= (I • t)/V
PIC18F87J90 FAMILY
This measured value is then stored and used for
calculations of time measurement or subtracted for
capacitance measurement. For calibration, it is
expected that the capacitance of C
approximately known; C
An iterative process may need to be used to adjust the
time, t, that the circuit is charged to obtain a reasonable
voltage reading from the A/D Converter. The value of t
may be determined by setting C
value, then solving for t. For example, if C
theoretically calculated to be 11 pF, and V is expected
to be 70% of V
or 63 s.
See Example 24-3 for a typical routine for CTMU
capacitance calibration.
(4 pF + 11 pF) • 2.31V/0.55 A
DD
, or 2.31V, then t would be:
AD
is approximately 4 pF.
OFFSET
DS39933D-page 315
STRAY
to a theoretical
+ C
STRAY
AD
is
is