MA180025 Microchip Technology, MA180025 Datasheet - Page 421

• Manufacturer Part Number: MA180025
• Description: MODULE PLUG-IN PIC18F87J90 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180025

• Accessory Type: Plug-In Module (PIM) - PIC18F87J90
• Product: Microcontroller Modules
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PICDEM LCD 2 Demonstration Board (DM163030)
• For Use With: DM163030 - KIT DEV PICDEM LCD2
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 28-14:
TABLE 28-19: I
 2010 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1:
Param.
No.
2:
Note:
T
T
T
T
T
T
T
T
T
T
T
C
SCL
SDA
In
SDA
Out
Symbol
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
B
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode I
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,
T
is released.
R
:
:
:
:
:
STA
DAT
STO
STA
DAT
max. + T
Refer to Figure 28-3 for load conditions.
2
Clock High Time
Clock Low Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Setup Time 100 kHz mode
Start Condition Hold Time
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time 100 kHz mode
Output Valid from Clock
Bus Free Time
Bus Capacitive Loading
C™ BUS DATA REQUIREMENTS (SLAVE MODE)
SU
I
2
90
2
:
C™ BUS DATA TIMING
DAT
C™ bus device can be used in a Standard mode I
103
= 1000 + 250 = 1250 ns (according to the Standard mode I
91
Characteristic
109
100 kHz mode
400 kHz mode
MSSP Module
100 kHz mode
400 kHz mode
MSSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100
106
101
109
PIC18F87J90 FAMILY
20 + 0.1 C
20 + 0.1 C
107
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
2
C bus system, but the requirement, T
B
B
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus specification), before the SCL line
Units
pF
s
s
s
s
ns
ns
ns
ns
s
s
s
s
ns
s
ns
ns
s
s
ns
ns
s
s
C
10 to 400 pF
C
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free before
a new transmission can start
92
B
B
102
is specified to be from
is specified to be from
110
Conditions
DS39933D-page 421
SU
:
DAT
 250 ns,