MA180025 Microchip Technology, MA180025 Datasheet - Page 243

MODULE PLUG-IN PIC18F87J90 PIM

MA180025

Manufacturer Part Number
MA180025
Description
MODULE PLUG-IN PIC18F87J90 PIM
Manufacturer
Microchip Technology
Series
PIC®r
Datasheets

Specifications of MA180025

Accessory Type
Plug-In Module (PIM) - PIC18F87J90
Product
Microcontroller Modules
Silicon Manufacturer
Microchip
Core Architecture
PIC
Core Sub-architecture
PIC18
Silicon Core Number
PIC18F
Silicon Family Name
PIC18FxxJxx
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
PICDEM LCD 2 Demonstration Board (DM163030)
For Use With
DM163030 - KIT DEV PICDEM LCD2
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MA180025
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
MA180025
Manufacturer:
MICROCHIP
Quantity:
12 000
18.4.8
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and starts
its count. If SCL and SDA are both sampled high when
the Baud Rate Generator times out (T
pin is driven low. The action of the SDA pin being driven
low while SCL is high is the Start condition and causes
the S bit (SSPSTAT<3>) to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resumes its count. When the Baud
Rate Generator times out (T
(SSPCON2<0>) will be automatically cleared by
hardware. The Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
FIGURE 18-21:
 2010 Microchip Technology Inc.
I
CONDITION TIMING
2
C MASTER MODE START
Write to SEN bit occurs here
FIRST START BIT TIMING
SDA
SCL
BRG
), the SEN bit
BRG
), the SDA
SDA = 1,
SCL = 1
T
BRG
Set S bit (SSPSTAT<3>)
T
S
BRG
PIC18F87J90 FAMILY
At completion of Start bit,
hardware clears SEN bit
18.4.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL bit is set and the contents of
the buffer are unchanged (the write doesn’t occur).
and sets SSPIF bit
Note:
Note:
T
Write to SSPBUF occurs here
BRG
If, at the beginning of the Start condition,
the SDA and SCL pins are already
sampled low, or if during the Start condi-
tion, the SCL line is sampled low before
the SDA line is driven low, a bus collision
occurs. The Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is aborted
and the I
state.
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
1st bit
WCOL Status Flag
T
BRG
2
C module is reset into its Idle
2nd bit
DS39933D-page 243

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