MA180025 Microchip Technology, MA180025 Datasheet - Page 286

• Manufacturer Part Number: MA180025
• Description: MODULE PLUG-IN PIC18F87J90 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180025

• Accessory Type: Plug-In Module (PIM) - PIC18F87J90
• Product: Microcontroller Modules
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PICDEM LCD 2 Demonstration Board (DM163030)
• For Use With: DM163030 - KIT DEV PICDEM LCD2
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J90 FAMILY
20.4.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA2<5>), or the Continuous Receive
Enable bit, CREN (RCSTA2<4>). Data is sampled on
the RX2 pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
FIGURE 20-8:
TABLE 20-7:
DS39933D-page 286
INTCON
PIR3
PIE3
IPR3
RCSTA2
RCREG2 AUSART Receive Register
TXSTA2
SPBRG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Name
Note:
Initialize the SPBRG2 register for the appropriate
baud rate.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
Ensure bits, CREN and SREN, are clear.
RX2/DT2 pin
TX2/CK2 pin
(Interrupt)
CREN bit
RC2IF bit
RCREG2
bit SREN
SREN bit
Write to
Timing diagram demonstrates Sync Master mode with bit, SREN = 1, and bit, BRGH = 0.
Read
AUSART SYNCHRONOUS
MASTER RECEPTION
AUSART Baud Rate Generator Register
GIE/GIEH PEIE/GIEL
Q2
CSRC
SPEN
Bit 7
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
—
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
LCDIF
LCDIE
LCDIP
Bit 6
RX9
TX9
bit 0
TMR0IE
RC2IF
RC2IE
RC2IP
SREN
TXEN
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
bit 2
INT0IE
CREN
TX2IF
TX2IE
TX2IP
SYNC
Bit 4
bit 3
CTMUIE
CTMUIP
CTMUIF
ADDEN
RBIE
Bit 3
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
—
If interrupts are desired, set enable bit, RC2IE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
Interrupt flag bit, RC2IF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RC2IE, was set.
Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG2 register.
bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
TMR0IF
CCP2IF
CCP2IE
CCP2IP
BRGH
FERR
Bit 2
bit 5
CCP1IE
CCP1IP
CCP1IF
INT0IF
OERR
TRMT
bit 6
Bit 1
 2010 Microchip Technology Inc.
RTCCIE
RTCCIP
RTCCIF
bit 7
RX9D
TX9D
RBIF
Bit 0
Q1 Q2 Q3 Q4
on Page
Values
Reset
59
62
62
62
64
64
64
64
‘0’