AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 285

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6048B–ATARM–29-Jun-06
Note:
Note:
• When a receiver detects a dominant bit as the first bit after sending an error flag, the
• When a transmitter sends an error flag, the transmit error count is increased by 8 except:
• If a transmitter detects a bit error while sending an active error flag or an overload flag, the
• If a receiver detects a bit error while sending an active error flag or an overload flag, the
• Any node tolerates up to 7 consecutive dominant bits after sending an active error flag,
• After the successful transmission of a message (getting ACK and no error until end of
• After the successful reception of a message (reception without error up to the ACK slot and
• A node is error passive when the transmit error count equals or exceeds 128, or when the
• A node is bus off when the transmit error count is greater than or equal to 256.
• An error passive node becomes error active again when both the transmit error count and
• An node that is bus off is permitted to become error active (no longer bus off) with its error
receive error count will be increased by 8.
In case of one of these exceptions, the transmit error count is not changed.
transmit error count is increased by 8.
receive error count is increased by 8.
passive error flag or overload flag. After detecting the 14th consecutive dominant bit (in
case of an active error flag or an overload flag) or after detecting the 8th consecutive
dominant bit following a passive error flag, and after each sequence of additional eight
consecutive dominant bits, every transmitter increases its transmit error count by 8 and
every receiver increases its receive error count by 8.
frame is finished), the transmit error count is decreased by 1 unless it was already 0.
the successful sending of the ACK bit), the receive error count is decreased by 1, if it was
between 1 and 127. If the receive error count was 0, it stays 0, and if it was greater than
127, then it will be set to a value between 119 and 127.
receive error count equals or exceeds 128. An error condition letting a node become error
passive causes the node to send an active error flag.
the receive error count are less than or equal to 127.
counters both set to 0 after 128 occurrences of 11 consecutive recessive bits have been
monitored on the bus.
– if the transmitter is error passive and detects an acknowledgement error because
– if the transmitter sends an error flag because a stuff error occurred during
of not detecting a dominant ACK. It does not detect a dominant bit while sending
its passive error flag.
arbitration, and should never been recessive, and has been sent as recessive but
monitored as dominant
An error count value greater than 96 indicates a heavily disturbed bus. It may be useful to pro-
vide means to test for this condition.
Start-up/Wake-up: If during system start-up only one node is online, and if this node transmits a
message, it gets no acknowledgement, detects an error and repeats the message. It can
become error passive but not bus off due to this reason.
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