AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 272

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

25.2.5
25.2.6
25.2.7
25.2.8
25.2.9
25.2.10
25.2.10.1
25.2.10.2
272
AT91SAM7A1
Bit Rate
Priorities
Remote Data Request
Multi-master Function
Arbitration
Data Transfer Security
Error Detection
Performance of Error Detection
The speed of the CAN may be different in different systems. However, in a given system the
bit-rate is uniform and fixed.
The identifier defines a static message priority during bus access.
By sending a remote frame, a node requiring data may request another node to send the cor-
responding data frame. The data frame and the corresponding remote frame are named by
the same identifier.
When the bus is free, any unit may start transmitting a message. The unit with the message of
highest priority to be transmitted gains bus access.
Whenever the bus is free, any unit may start transmitting a message. If two or more units start
transmitting messages at the same time, the bus access conflict is resolved by bit-wise arbitra-
tion using the identifier. The mechanism of arbitration guarantees that neither information nor
time is lost. If a data frame and a remote frame with the same identifier are initiated at the
same time, the data frame prevails over the remote frame. During arbitration every transmitter
compares the level of the bit transmitted with the level that is monitored on the bus. If these
levels are equal the unit may continue to send. When a recessive level is sent and a dominant
level is monitored (see
draw without sending one more bit.
In order to achieve the utmost security of data transfer, powerful measures for error detection,
signalling and self-checking are implemented in every CAN node.
For detecting errors, the following methods are used:
The error detection mechanisms have the following properties:
• Multicast: As a consequence of the message filtering, any number of nodes can receive
• Data consistency: Within a CAN network, it is guaranteed that a message is simultaneously
• Monitoring (transmitters compare the bit levels to be transmitted with the bit levels detected
• Cyclic Redundancy Check (CRC)
• Bit stuffing
• Message frame check
• All global errors are detected by means of monitoring.
and simultaneously act upon the same message.
accepted either by all nodes or by no node. Thus, data consistency of a system is achieved
by the concepts of multicast and by error handling.
on bus)
”Bus Values” on page
273), the unit has lost arbitration and must with-
6048B–ATARM–29-Jun-06