AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 245

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.6.19
Name:
Access:
Address:
Note:
• RDRF: Receive Data Register Full
0: No data has been received since the last read of SPI_RDR.
1: A data has been received and the receive data has been transferred from the serializer in SPI_RDR since the last read
of SPI_RDR.
• TDRE: Transmit Data Register Empty
0: Data has been written in SPI_TDR and not yet transferred to the serializer.
1: The last data written in the Transmit Data Register has been transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0: No Mode Fault has been detected since the last read of SPI_SR.
1: A Mode Fault occurred since the last read of SPI_SR.
• SPIOVRE: Overrun Error
0: No overrun has been detected since the last read of SPI_SR.
1: An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• REND: Reception End
0: No reception or reception processing.
1: End of reception.
• TEND: Transfer End
0: No transfer or transfer processing.
1: End of transfer.
• SPIENS: SPI Enable
0: SPI is disabled.
1: SPI is enabled.
6048B–ATARM–29-Jun-06
31
23
15
–
–
–
7
–
This register is a “read-active” register, which means that reading it can affect the state of some bits. When reading SPI_SR reg-
ister, following bits are cleared if set: MODF, SPIOVRE, REND, TEND, SPCK, MISO, MOSI, NPCS0, NPCS1, NPCS2 and
NPCS3.
SPI Status Register
SPI_SR
Read-only
0xFFFB4070
NPCS3
30
22
14
–
–
6
–
NPCS2
TEND
29
21
13
–
–
5
NPCS1
REND
28
20
12
–
–
4
SPIOVRE
NPCS0
27
19
11
–
–
3
MODF
MOSI
26
18
10
–
–
2
AT91SAM7A1
TDRE
MISO
25
17
–
9
–
1
SPIENS
RDRF
SPCK
24
16
–
8
0
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