AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 113

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 16-2. GIC Automatic Vectoring
16.1.2
16.1.3
6048B–ATARM–29-Jun-06
0x0000001C
0x0000000C
0x00000018
0x00000014
0x00000010
0x00000008
0x00000004
0x00000000
Priority Controller
Software Interrupt Handling
Address Exception (26-bit)
LDRpc,[pc,#&F20] (FIQ)
LDRpc,[pc,#&F20] (IRQ)
Undefined Instruction
Software Interrupt
Prefetch Abort
Data Abort
Reset
The nIRQ line is controlled by an 8-level priority encoder. Each source has a programmable
priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest.
When the GIC receives more than one unmasked interrupt at a time, the interrupt with the
highest priority is serviced first. If both interrupts have equal priority, the interrupt with the low-
est interrupt source number is serviced first (see
The current priority level is defined as the priority level of the current interrupt at the time the
register GIC_IVR is read (the interrupt which will be serviced).
If a higher priority unmasked interrupt occurs while an interrupt already exists, there are two
possible outcomes depending on whether the GIC_IVR has been read.
When the end of interrupt command register (GIC_EOICR) is written, the current interrupt
level is updated with the last stored interrupt level from the stack (if any). Hence at the end of
a higher priority interrupt, the GIC returns to the previous state corresponding to the preceding
lower priority interrupt which had been interrupted.
The interrupt handler must read the GIC_IVR as soon as possible. This de-asserts the nIRQ
request to the processor and clears the interrupt in case it is programmed to be edge trig-
gered. This permits the GIC to assert the nIRQ line again when a higher priority unmasked
interrupt occurs.
At the end of the interrupt service routine, the end of interrupt command register (GIC_EOICR)
must be written. This allows pending interrupts to be serviced.
• If the nIRQ line has been asserted but the GIC_IVR has not been read, then the processor
• If the processor has already read the GIC_IVR then the nIRQ line is reasserted. When the
reads the new higher priority interrupt handler address in the GIC_IVR register and the
current interrupt level is updated.
processor has authorized nested interrupts to occur and reads the GIC_IVR again, it reads
the new higher priority interrupt handler address. At the same time the current priority value
is pushed onto a first-in last-out stack and the current priority is updated to the higher
priority.
0xFFFFF104
0xFFFFF100
GIC_FVR
GIC_IVR
Index
Table 16-1 on page
GIC_SVR30
GIC_SVT31
GIC_SVR2
GIC_SVR1
GIC_SVR0
...
AT91SAM7A1
111).
@ of interrupt
@ of interrupt
subroutine 31
subroutine 0
(FIQ)
113