AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 149

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 18-5. Synchronous Mode, Character Reception
18.4.3
18.4.4
18.4.5
18.4.6
18.4.7
6048B–ATARM–29-Jun-06
Example: 8-bit parity enabled, 1 stop
Sampling
RXD
SCK
Receiver Ready
Parity Error
Framing Error
Idle Flag for J1587 Protocol Frame
Time-out
True Start Detection
D0
When a complete character is received, it is transferred to the US_RHR and the RXRDY sta-
tus bit in US_SR is set. The RXRDY is set after the last stop bit.
If US_RHR has not been read since the last transfer, the USOVRE status bit in US_SR is set.
Each time a character is received, the receiver calculates the parity of the received data bits,
in accordance with the PAR field in US_MR. It then compares the result with the received par-
ity bit. If different, the parity error bit PARE in US_SR is set.
If a character is received with a stop bit at low level and with at least one data bit at high level,
a framing error is generated. This sets FRAME in US_SR.
The idle flag turns low when the USART receives a start bit and turns high at the end of a
J1587 protocol frame (after 10 stop bits). An interrupt can be generated on the rising edge of
the idle flag.
Figure 18-6. Idle Flag
The time-out function allows an idle condition on the RXD line to be detected. The maximum
delay for which the USART should wait for a new character to arrive while the RXD line is inac-
tive (high level) is programmed in US_RTOR (Receiver Time-out Register). When this register
is set to 0, no time-out is detected.
Otherwise, the receiver waits for a first character and then initializes a counter which is decre-
mented at each bit period and reloaded at each byte reception. When the counter reaches 0,
the TIMEOUT bit in US_SR is set. The user starts (or restarts) the wait for a first character by
setting the STTTO (start time-out) bit in US_CR.
RX
Idle_Flag
or Not Busy
USART IRQ
D1
D2
MID
D3
PID
D4
Dum
D5
PID
D6
Data
D7
Data
Parity Bit
AT91SAM7A1
ChkSum
Stop Bit
10 Stop Bits
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