AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 243

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.6.18
Name:
Access:
Address:
• MSTR: Master/Slave Mode
0: SPI is in Slave Mode. The SPI in Slave Mode can not be used with the PDC for data transmission or reception.
1: SPI is in Master Mode.
MSTR configures the SPI for either master or Slave Mode operation.
• PS: Peripheral Select
0: Fix peripheral select.
1: Variable peripheral select.
The peripheral mode is only used in Master Mode. In case of fix peripheral select, the selected peripheral is defined in the
mode register. For variable peripheral select, it is defined in the transmit data register.
• PCSDEC: Chip Select Decode
0: The chip selects are directly connected to a peripheral device.
1: The four chip select lines are connected to a 4-to-16 decoder.
In case PCSDEC is one, up to 16 Chip Select signals can be generated with the four lines using an external 4 to 16
decoder.
The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:
• DIV32: Clock Selection
0: SPI Master Clock equals CORECLK.
1: SPI Master Clock equals CORECLK/32.
• LLB: Local Loopback
0: Local loopback path disabled.
1: Local loopback path enabled.
LLB controls the local loopback on the data serializer for testing.
6048B–ATARM–29-Jun-06
– SPI_CSR0 defines peripheral chip select signals 0 to 3.
– SPI_CSR1 defines peripheral chip select signals 4 to 7.
– SPI_CSR2 defines peripheral chip select signals 8 to 11.
– SPI_CSR3 defines peripheral chip select signals 12 to 15.
LLB
31
23
15
–
–
7
SPI Mode Register
SPI_MR
Read/Write
0xFFFB4064
30
22
14
–
–
6
–
29
21
13
–
–
5
–
28
20
12
–
–
4
–
DLYBCS
DIV32
27
19
11
–
3
PCSDEC
26
18
10
–
2
PCS
AT91SAM7A1
PS
25
17
9
–
1
MSTR
24
16
8
–
0
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