AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 151

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.6
18.6.1
18.6.2
18.6.3
18.6.4
6048B–ATARM–29-Jun-06
Break Condition
Transmit Break
Receive Break
Interrupt Generation
Channel Modes
Figure 18-7. Synchronous and Asynchronous Modes, Character Transmission
The transmitter can generate a break condition on the TXD line when the STTBRK command
is set in US_CR (Control Register). In this case, the characters present in US_THR and in the
Transmit Shift Register are completed before the line is held low.
To remove this break condition on the TXD line, the STPBRK command in US_CR must be
set. The USART generates a minimum break duration of one character length.
The TXD line then returns to high level (idle state) for at least 12 bit periods to ensure that the
end of break is correctly detected. The transmitter then resumes normal operation.
The break condition is detected by the receiver when all data, parity and stop bits are low. At
the moment of the low stop bit detection, the receiver asserts the RXBRK bit in US_SR.
The end of receive break is detected by a high level for at least 2/16 of the bit period in asyn-
chronous operating mode or at least one sample in synchronous operating mode. RXBRK is
also set after end of break has been detected.
Each status bit in US_SR has a corresponding bit in US_IER (Interrupt Enable Register) and
US_IDR (Interrupt Disable Register) which controls the generation of interrupts by asserting
the USART interrupt line connected to the Generic Interrupt Controller. US_IMR (Interrupt
Mask Register) indicates the status of the corresponding bits.
When a bit is set in US_SR and the same bit is set in US_IMR, the interrupt line is asserted.
The USART can be programmed to operate in three different test modes, using the CHMODE
field in US_MR.
Automatic Echo Mode provides bit-by-bit retransmission. When a bit is received on the RXD
line, it is sent to the TXD line. Programming the transmitter has no effect
Local Loopback Mode enables the transmitted characters to be received. TXD and RXD pins
are not used and the output of the transmitter is internally connected to the input of the
receiver. The RXD pin level has no effect and the TXD pin is held high, as in idle state.
Remote Loopback Mode directly connects the RXD pin to the TXD pin. The Transmitter and
the Receiver are disabled and have no effect. This mode provides bit by bit retransmission.
Baud Rate
Example: 8-bit, parity enabled, 1 stop
Clock
TXD
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
AT91SAM7A1
Parity Bit
Stop Bit
151