AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 64

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.1.3
Name:
Access:
Address:
• PLLSLCT: PLL/Master Clock Selection
0: Selects MCK clock (deselects PLLCLK or PLLCLK/2 clock).
1: Selects PLLCLK or PLLCLK/2 clock (deselects MCK clock).
• LFSLCT: Low Frequency Clock Selection
0: Allows selection of MCK, PLLCLK, PLLCK/2 or DIVCLK.
1: Selects low frequency clock LFCLK (also disables master clock oscillator and PLL).
• DIVSLCT: Programmable Clock Selection
0: Allows selection of MCK, PLLCK or PLLCLK/2 (also deselects the DIVCLK clock).
1: Selects DIVCLK, i.e. MCK divided by MDIV[6:0] (also deselects the master clock or PLL clock).
• RTCSEL: RTC frequency clock selection
0: Selects the DIVCLK clock for low power clock (deselects the RTCK clock).
1: Selects the RTCK clock for low power clock (deselects the DIVCLK clock).
• RTCKEN: Low Frequency Clock Oscillator
0: The low frequency clock oscillator is disabled.
1: The low frequency clock oscillator is enabled.
• MCKEN: Master Clock Oscillator Enable
0: MCKEN signal is at a logical 0. The master clock oscillator is disabled and bypassed.
1: MCKEN signal is at a logical 1. The master clock oscillator is activated.
• PLLEN: PLL Enable
0: PLLEN signal is at a logical 0. PLL is deactivated.
1: PLLEN signal is at a logical 1. PLL is enabled.
64
RTCKEN
31
23
15
–
–
–
7
AT91SAM7A1
CM Clock Status Register
CM_CS
Read-only
0xFFFEC008
RTCSLCT
RTCSEL
30
22
14
–
–
6
DIVSLCT
DIVEN
29
21
13
–
–
5
28
20
12
–
–
–
4
–
LFSLCT
27
19
11
–
–
–
3
PLLSLCT
26
18
10
–
–
–
2
PLLEN
25
17
–
–
9
1
–
6048B–ATARM–29-Jun-06
MCKEN
24
16
–
–
8
0
–