AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 196

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

20. Simple Timer (ST)
The AT91SAM7A1 microcontroller includes two 16-bit Simple Timers (ST0 and ST1) with 2
channels per simple timer.
Each simple timer channel provides basic functions for timing calculation including two cas-
caded dividers and a 16 bit-counter.
The prescalar defines the clock frequency of the channel counter.
For each channel it is possible to select the divider clock between the core clock (CORECLK)
and the low frequency clock (LFCLK).
The 16-bit counter starts down-counting when a value different from zero is loaded. An inter-
rupt is generated when the counter reaches 0x0000.
When a value is loaded in the LOAD[15:0] bits of the STx_CTz register and the channel is
started, the counter starts down-counting at channel clock frequency until the counter reaches
zero. The delay between the load and the interrupt is:
Counter Value x Clock Period
The counter value is the value loaded in the counter. The clock period is the period of the
channel clock (divided by the prescalar).
The precision is one clock period (from 0 to 1 channel clock period lost).
When enabling or disabling the Simple Timer, software must wait for enabled or disabled inter-
rupt (or status) to be sure that the counter is really enabled or disabled (it is asynchronously
clocked).
It is not possible to change contents of the Channel X Counter Register when the Simple
Timer is enabled.
If a channel is disabled before it finishes down-counting, the counter value is held. If no write
has occurred on the Counter Register before it is re-enabled, the down-counting restarts from
the latest counter value.
When the core clock (CORECLK) is selected on the Prescalar Register, the clock is divided
twice to obtain the counter clock. First, it is divided by a divider driven by the SYSCAL bits of
the Prescalar Register, and then by a divider driven by the prescalar bits of the Prescalar
Register.
On the other hand, if the low frequency clock (LFCLK) is selected, the clock is divided only
once to obtain the counter clock. In this case, it is divided by a divider driven by the prescalar
bits of the Prescalar Register.
The Simple Timer also integrates an automatic reload function if the AUTOREL bit is set on
the corresponding STx_PRz register. When the counter reaches 0x0000, it is automatically
reloaded with the value written in LOAD[15:0] bits of the STx_CTz registers (x for ST0 or ST1
and z for channel 0 or channel 1).
The current value of the counter can be read in the corresponding ST_CCVx register.
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