AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 150

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.5
18.5.1
18.5.2
150
Transmitter
AT91SAM7A1
Time-guard
Multidrop Mode
To start a time-out, the following conditions must be met:
Moreover, it should be noted that writing STTTO in US_CR is taken into account under the two
following conditions:
Calculation of time-out duration in asynchronous mode:
The transmitter has the same behavior in both synchronous and asynchronous operating
modes. Start bit, data bits, parity bit and stop bits are serially shifted, least significant bit first,
on the falling edge of the serial clock.
The number of data bits is selected in the CHRL field in US_MR.
The parity bit is set according to the PAR field in US_MR.
The number of stop bits is selected in the NBSTOP field in US_MR.
When a character is written to US_THR (Transmit Holding Register), it is transferred to the
Shift Register as soon as it is empty.
When the transfer occurs, the TXRDY bit in US_SR is set until a new character is written to
US_THR. If the Transmit Shift Register and US_THR are both empty, the TXEMPTY bit in
US_SR is set (after the last stop bit of the last transfer).
The time-guard function allows the transmitter to insert an idle state on the TXD line between
two characters. The duration of the idle state is programmed in US_TTGR (Transmitter Time-
guard Register). When this register is set to zero, no time-guard is generated. Otherwise, the
transmitter holds a high level on TXD after each transmitted byte during the number of bit peri-
ods programmed in US_TTGR.
When the PAR field in US_MR equals 11X
mode. In this case, the parity error bit (PARE in US_SR) is set when data is detected with a
parity bit set to identify an address byte. PARE is cleared with the Reset Status Bits Command
(RSTSTA) in US_CR. If the parity bit is detected low, identifying a data byte, PARE is not set.
The transmitter sends an address byte (parity bit set) when a Send Address Command
(SENDA) is written to US_CR.
In this case, the next byte written to US_THR will be transmitted as an address. After this, any
byte transmitted has the parity bit cleared.
• US_RTOR must not be equal to 0.
• The time-out must be started by setting STTTO to a logical 1 in the US_CR register.
• One character must be received.
• Baud rate is set to a value different from '0' (in order to clock the receiver state machine)
• Receiver state machine is reset
Duration = Value x 4 x Bit period.
Idle state duration between two characters = Time-guard Value x Bit Period
b
, the USART is configured to run in multidrop
6048B–ATARM–29-Jun-06