AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 288

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

25.11.9
25.11.10 Hard Synchronization
25.11.11 Resynchronization Jump Width
288
AT91SAM7A1
Length of Time Segments
In other words, the time after the sample point that is needed to calculate the next bit to be
sent (e.g., data bit, CRC bit, stuff bit, error flag, or idle) is called the Information Processing
Time (IPT).
The CAN module has zero delay IPT.
The total number of time quanta in a bit time is programmable at least from 8 to 25.
Note:
The position of the sample point, however, should be selected in common for all nodes. There-
fore, the bit timing of CAN devices without local CPU should be compatible with the definition
of the bit time in
Figure 25-15. Example of Nominal Bit Time
After a hard synchronization, the internal bit time is restarted with SYNC_SEG. Thus hard syn-
chronization forces the edge that caused the hard synchronization to lie within the
synchronization segment of the restarted bit time.
As a result of resynchronization, PHASE_SEG1 may be lengthened or PHASE_SEG2 may be
shortened. The amount of lengthening or shortening of the phase buffer segments has an
upper bound given by the resynchronization jump width. The resynchronization jump width is
programmable between 1 and min(4, PHASE_SEG1).
Clocking information may be derived from transitions from one bit value to the other. The prop-
erty that only a fixed maximum number of successive bits have the same value provides the
possibility of resynchronizing a bus unit to the bit stream during a frame. The maximum length
between two transitions that can be used for resynchronization is 29 bit times.
• SYNC_SEG is 1 time quantum long.
• PROP_SEG is programmable to be between 1 and 8 time quanta long.
• PHASE_SEG1 is programmable to be between 1 and 8 time quanta long.
• PHASE_SEG2 is the maximum of PHASE_SEG1 and the information processing time.
• The information processing time is 0 time quanta long.
It is often intended that control units do not make use of different oscillators for the local CPU
and its communication device. Therefore, the oscillator frequency of a CAN device tends to be
that of the local CPU and is determined by the requirements of the control unit. In order to
derive the desired bit rate, programmability of the bit timing is necessary. In case of CAN imple-
mentations that are designed for use without a local CPU, the bit timing cannot be
programmable. On the other hand, these devices allow selection of an external oscillator in such
a way that the device is adjusted to the appropriate bit rate so that the programmability is dis-
pensable for such components.
Quantum
1 Time
Figure
Quantum
1 Time
25-15.
Phase Buffer Seg 1
4 Time Quanta
10 Time Quanta
1 Bit Time
Phase Buffer Seg 2
4 Time Quanta
6048B–ATARM–29-Jun-06