AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 129

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6048B–ATARM–29-Jun-06
the master clock by 0 (ADC clock = CORECLK), 4, 8, …, 48, ..., 64, ..., 124. Thus, the ADC
clock is adapted as much as possible to a master clock comprised between 500 kHz and 40
MHz. For example, if CORECLK = 30 MHz with a preload value of 60, the ADC clock is 500
kHz.
A single conversion at the maximum clock rate permitted (i.e., 500 kHz) occurs in 22.0 µs.
The IES bit in the ADC mode register is used to select whether the conversion starts with a
software start or with an external trigger start.
The signal that starts the conversion is selected by the IES bit in the ADC Mode Register
(ADC_MR).
Writing 1 to the START bit starts the conversion even if the analog structure begins the con-
version when start goes low. In this case, the interface transmits the opposite of the start
command to the analog part.
For a conversion, different input combinations can be selected. NBRCH[2:0] indicates how
many inputs will be converted (the real number is the value of NBRCH incremented by one).
The result of the conversion is stored in the Convert Data Register (ADC_DR). When the con-
version is complete, the analog part activates the EOC bit in the ADC Status Register
(ADC_SR) and sends an EOC signal to the PDC which then takes the result and writes to a
memory location. The EOC bit in ADC_SR (Status Register) is cleared when the ADC_DR
(Convert Data Register) is read. If a new result arrives before the PDC or the CPU read the old
data, the Overrun bit (OVR) is set active to specify to the microprocessor that data is lost. If the
PDC is used to save the results and if the transfer of all the data is finished, the PDC sets the
TEND bit to a logical 1. The TEND bit and the OVR bit are reset when the status register
(ADC_SR) is read.
The READY bit is set after an absolute time of 4 µs after an enable command, which corre-
sponds to the initialization time of the analog part. This time is necessary to stabilize the
analog structure and does not depend on the choice of the ADC clock or the names of analog
inputs considered. The number of master clock periods necessary to wait during 4 µs is mem-
orized in the STARTUPTIME bits of the mode register.
The user can make continuous conversions. This status is indicated by the CONTCV bit of the
ADC Mode Register (ADC_MR). In this case, the microprocessor or an external command
gives the first start to the ADC and the peripheral does not stop the conversion until the STOP
bit of the ADC Control Register is set, or when the TEND bit of the status register is set if
STOPEN is active. The digital interface between the analog part and the APB bus is in standa-
lone mode; this permits conversion without any help. This mode can be associated with
multiple conversion as well as single conversion. The different steps of the conversion are
equivalent to those of a single conversion.
• If IES = 0, the ADC starts the conversion by writing 1 in the START bit of the control register
• If IES = 1, the bit START of the control register is ignored and the conversions starts as
(ADC_CR).
soon as a rising edge occurs on the external pin; the signal has to be high during at least
one period of the CORECLK, else it is impossible to detect a rising edge.
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