AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 290

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

25.12 Reception Mode
25.13 Time Stamp
25.14 Power Management
25.15 Example of Use
25.15.1
25.15.1.1
25.15.1.2
290
AT91SAM7A1
Message Transmission
Processing Transmission Request Delay
Warning on Frame Transmission Modification
In reception, channels can be configured in two different modes:
A 32-bit stamp dates all messages sent/received (depending on the producer/consumer bit).
The 32-bit register forming the second counter in the WT module is provided to the CAN mod-
ule. After each transmission or reception of a CAN frame, the value of the current second
counter is automatically written in the corresponding CAN channel CAN_STPx register.
The CAN is provided with a power management block allowing optimization of power con-
sumption (see
When a CAN channel configured in transmission is enabled, the transmission of the frame
does not start immediately but after a short delay. This delay is due to channel scanning.
When the bus is idle, the CAN state machine continually scans all channels, looking for trans-
mit channels. During a scanning cycle - starting from channel 0 and ending at channel 15 or
31 - if several channels are configured in transmission, the CAN state machine memorizes the
channel with the lowest identifier, and at the end of the scanning cycle it starts the transmis-
sion of the highest priority frame.
Scanning delay of CAN channels depends on the channel state: a channel enabled and con-
figured in transmission is scanned in three system clock periods, otherwise it takes 2 system
clock periods. Then, scanning all the channels takes at maximum 49 system clock periods for
a 16-channel CAN and 97 system clock periods for a 32-channel CAN.
As the CPU may enable a transmit channel at any moment during the scanning cycle, the
delay from the moment the channel is enabled by the CPU to the moment the frame starts to
be transmitted may be unsettled and can take at maximum two times the delay for scanning all
channels. Moreover, as the scan of the channels is also asynchronous with the bit time,
between 0 and 1 bit times should be added to this delay.
Once a transmission has been requested, users should not modify the frame to transmit
(CAN_IRX,CAN_DRAX, CAN_DRBX and CAN_CRX registers) until the transmission is com-
pleted (flag TXOK set to ‘1’ in the CAN_SRx register). In order to modify a frame to transmit,
users should cancel the transmission, change the frame and then request a new transmission.
Find below how to cancel a transmission.
• Normal mode (OVERWRITE bit reset to 0 in CAN_CRx): the channel is disabled after a
• Overwrite mode (OVERWRITE bit set to 1 in CAN_CRx): the channel is still enabled after a
successful reception.
successful reception.
”Power Management Block” on page
23).
6048B–ATARM–29-Jun-06