AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 114

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

16.1.4
16.1.5
16.1.6
16.1.7
16.1.8
16.2
114
Standard Interrupt Sequence
AT91SAM7A1
Interrupt Masking
Interrupt Clearing and Setting
Fast Interrupt Request
Software Interrupt
Spurious Interrupt
Each interrupt source, including FIQ, can be enabled or disabled using the command registers
GIC_IECR and GIC_IDCR. The interrupt mask can be read in the read only register GIC_IMR.
A disabled interrupt does not affect the servicing of other interrupts.
All interrupt sources which are programmed to be edge triggered (including FIQ) can be indi-
vidually set or cleared by writing to the registers GIC_ISCR and GIC_ICCR, respectively. This
function of the interrupt controller is available for auto-test or software debug purposes.
The external FIQ line is the only source which can raise a fast interrupt request to the proces-
sor. Therefore it has no priority controller. It can be programmed to be positive or negative
edge triggered or high or low level sensitive in the GIC_SMR0 register.
The fast interrupt handler address can be stored in the GIC_SVR0 register. The value written
into this register is available by reading the GIC_FVR register when an FIQ interrupt is raised.
By storing the following instruction at address 0x0000001C, the processor will load the pro-
gram counter with the interrupt handler address stored in the GIC_FVR register.
Alternatively, the interrupt handler can be stored starting from address 0x0000001C as
described in the ARM7TDMI datasheet.
Any interrupt source of the GIC can be a software interrupt. It must be programmed to be edge
triggered in order to set or clear it by writing to the GIC_ISCR and GIC_ICCR. This is totally
independent of the SWI instruction of the ARM7TDMI processor.
A spurious interrupt is a signal of very short duration on one of the interrupt input lines.
For details on the registers mentioned in the steps below, refer to the ARM7TDMI Embedded
Core Datasheet.
It is assumed that:
When nIRQ is asserted, if the bit I of CPSR is 0, the sequence is:
• The Generic Interrupt Controller has been programmed, GIC_SVR are loaded with
• The Instruction at address 0x18 (IRQ exception vector address) is: ldr pc, [pc, #-&F20].
1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded
2. The ARM core enters IRQ mode, if it is not already.
3. When the instruction loaded at address 0x18 is executed, the Program Counter is
corresponding interrupt service routine addresses and interrupts are enabled.
in the IRQ link register (r14_irq) and the Program Counter (r15) is loaded with 0x18.
In the following cycle during fetch at address 0x1C, the ARM core adjusts r14_irq,
incrementing it by 4.
loaded with the value read in GIC_IVR. Reading the GIC_IVR has the following
effects:
ldr PC,[PC,# -&F20]
6048B–ATARM–29-Jun-06