AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 148

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.4
18.4.1
Figure 18-3. Asynchronous Mode Start Bit Detection
Figure 18-4. Asynchronous Mode Character Reception
18.4.2
148
16 x Baud Rate
Example: 8-bit parity enabled, 1 stop
Sampling
RXD
Sampling
Receivers
AT91SAM7A1
Asynchronous Receiver
Synchronous Receiver
Clock
RXD
True Start Detection
Period
0.5-bit
Period
1-bit
The USART is configured with two receiver operating modes, one for asynchronous opera-
tions and the other for synchronous operations.
The USART is configured for asynchronous operation when SYNC = 0 (bit 7 of US_MR). In
asynchronous mode, the USART detects the start of a received character by sampling the
RXD signal until it detects a valid start bit. A low level (space) on RXD is interpreted as a valid
start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the
baud rate. Hence, a space longer than 7/16 of the bit period is detected as a valid start bit. A
space that is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a
valid start bit.
When a valid start bit has been detected, the receiver samples RXD at the theoretical mid-
point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (one bit
period), so the sampling point is 8 cycles (0.5 bit periods) after the start of the bit. The first
sampling point is therefore 24 cycles (1.5 bit periods) after the falling edge of the start bit.
Each subsequent bit is sampled 16 cycles (1 bit period) after the previous one.
When configured for synchronous operation (SYNC = 1), the receiver samples the RXD signal
on each rising edge of SCK. If a low level is detected, it is considered as a start. Data bits, par-
ity bit and stop bit are sampled and the receiver waits for the next start bit. See
D0
D1
D2
True Start
Detection
D3
D4
D5
D6
D7
Parity Bit
Stop Bit
6048B–ATARM–29-Jun-06
D0
Figure
18-5.