AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 361

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

26.12.6
Name:
Access:
Offset:
Note:
• COVFS: Counter Overflow Status
This bit is set when a counter overflow is detected. An overflow occurs when the counter reaches its maximal value 0xFFFF
(2
0: No overflow detected
1: Overflow detected since last read of GPTX_SR
• CPAS: Compare Register A Status
This bit is set when the counter reaches the register A value.
0: Compare A condition has not occurred since last read of GPTX_SR
1: Compare A condition has occurred since last read of GPTX_SR
• CPBS: Compare Register B Status
This bit is set when the counter reaches the register B value.
0: Compare B condition has not occurred since last read of GPTX_SR
1: Compare B condition has occurred since last read of GPTX_SR
• CPCS: Compare Register C Status
This bit is set when the counter reaches the register C value.
0: Compare C condition has not occurred since last read of GPTX_SR
1: Compare C condition has occurred since last read of GPTX_SR
• ETRGS: External Trigger Status
This bit is set when an external trigger is detected. An external trigger occurs with a valid edge (the edge polarity is set by
EEVTEDG[1:0] of the mode register) on the valid trigger pin (set by EEVT[1:0] of the mode register if ENETRG, bit 12 of the
Mode Register, is high).
0: External trigger not detected
1: External trigger detected since last read of GPTX_SR
• CLKSTA: Clock Status
0: Clock disabled
1: Clock enabled
6048B–ATARM–29-Jun-06
16
-1) and passes to 0x0000.
ETRGS
31
23
15
–
–
–
7
This register is a “read-active” register; thus, reading it can affect the state of some bits. When reading GPT_SR register, follow-
ing bits are cleared if set: COVFS, CPAS, CPBS, CPCS, ETRGS, TIOBS, TIOAS and TCLKS.
GPT Status Register in Waveform Mode
GPT_SR
Read-only
0x70
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
CPCS
28
20
12
–
–
–
4
CPBS
27
19
11
–
–
–
3
TCLKS
MTIOB
CPAS
26
18
10
–
2
AT91SAM7A1
MTIOA
TIOAS
25
17
–
9
1
–
CLKSTA
COVFS
TIOBS
24
16
–
8
0
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