AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 67

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.1.5
Name:
Access:
Address:
• PMUL[4:0]: PLL Multiplier
These bits select the PLL multiplier.
Note:
• PLLDIV2: PLL Divider
0: Selects PLLCLK clock (deselects PLLCLK/2)
1: Selects PLLCLK/2 clock (deselects PLLCLK)
• PDIVKEY[15:0]: Key for Write Access into the CM_PDIV Register
Any write in the PMUL[4:0] bits will only be effective if the PDIVKEY[15:0] is equal to 0x762D. These bits are always read at
0.
The output frequency of the PLL is equal to: MCK x PMUL[4:0], where MCK is the PLL input clock.
Note:
6048B–ATARM–29-Jun-06
PLLDIV2
31
23
15
7
–
Multiplying the MCK clock by 1 is equivalent to bypassing the PLL (i.e., CM_CS.2 = 0, CM_CS.3 = 0, CM_CS.5 = 0)
Write accesses to this register are only valid if PLLEN is at logical 0 (i.e., PLL disabled).
CM PLL Divider Register
CM_PDIV
Read/Write
0xFFFEC010
30
22
14
–
6
–
PMUL[4:0]
21 to 31
19
20
…
0
1
2
3
29
21
13
–
5
–
28
20
12
–
4
PDIVKEY[15:8]
PDIVKEY[7:0]
27
19
11
–
3
PMUL[4:0]
Remains in previous state
Remains in previous state
Remains in previous state
26
18
10
–
2
PLL Multiplier
19
20
…
2
3
AT91SAM7A1
25
17
9
–
1
(1)
24
16
8
–
0
67