AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 8

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5. Product Overview
5.1
5.1.1
5.1.2
5.1.3
5.1.3.1
5.1.3.2
8
Register Considerations
AT91SAM7A1
Enable/Disable/Status Registers
Example
Key Access to Registers
Example 1
Example 2
In order to reduce code size and subsequently increase speed when accessing internal
peripherals, most of the registers have been split into three address locations:
To set a bit to a logical 1 in the Status or Mask Register, a write command in the Enable or Set
Register must be performed with the corresponding bit at a logical 1.
To set a bit to a logical 0 in the Status or Mask Register, a write command in the Disable or
Clear Register must be performed with the corresponding bit at a logical 1.
Supposing that the US0_PSR register value is 0x00000000. To enable the RXD and SCK pins
as PIOs in the USART0 block, 0x00050000 must be written in the US0_PER register. The
value read in the US0_PSR register will be 0x00050000.
Now if the software wants to disable the RXD pin as a PIO (i.e. enable it for USART0 use), a
write access to the US0_PDR register with the value 0x00040000 must be performed. The
new value read in the US0_PSR register will be 0x00010000.
Some bits in registers can be set to a value (0 or 1) only if the right key is written at the same
time.
The TESTEN bit in the SFM_TM register can be set to a logical 0 or 1 only if the KEY[15:0] bits
are equal to 0xD64A.
To enable test mode, 0xD64A0002 must be written in the SFM_TM register.
To disable test mode, 0xD64A0000 must be written in the SFM_TM register.
To set the RTCKEN bit in the CM_CS register to logical 1, a write access to the CM_CE regis-
ter must be done with a value of 0x23050080.
To set the RTCKEN bit in the CM_CS register to logical 0, a write access to the CM_CD regis-
ter must be done with a value of 0x18070080.
• The first address location (Enable or Set Register) is used to set a bit to a logical 1.
• The second address location (Disable or Clear Register) is used to set a bit to a logical 0.
• The third address location (Status register or Mask Register) gives the current state of the
bit.
6048B–ATARM–29-Jun-06