AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 104

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

15.5.2
104
AT91SAM7A1
Reception on SPI
Assuming the following:
PDC channel 6 must be configured as follows:
As soon as the software writes the number of bytes to transfer in the PDC_TCR6 register, the
PDC starts receiving the 69 8-bit words.
When all the 8-bit words have been received (i.e., all bytes have been written in external
RAM), the REND bit in the SPI_SR register will be set to a logical 1 informing the software that
the transfer is completed. The REND bit in the SPI_SR register can also generate an interrupt
if the corresponding bit is set in the SPI_IMR register.
• SPI bits per transfer = 8 on NPCS0 (i.e., BITS[3:0] = 0000b in SPI_CRS0)
• Number of 8-bit words to transfer: 69
• Address of buffer in external RAM for 8-bit words to be transmitted 0x48000000 (first 8-bit
• SPI clock is enabled (SPI = 1 in SPI_PMSR)
• SPI is enabled (SPIENS = 1 in SPI_SR)
• PDC_PRA6 = 0xFFFB4080 (i.e., address of the SPI_RDR register)
• PDC_CR6 = 0x00000000 (i.e., 8-bit words cater in 8-bit words so PDC transfer size is a
• PDC_MPR6 = 0x48000000 (address of buffer in external RAM)
• PDC_TCR6 = 0x00000045 (number of 8-bit words to transfer)
word is at address 0x48000000, second 8-bit word is at address 0x48000001, etc.)
byte incrementing the address pointer by 1 after each transfer, transfers are done from
peripheral to memory so DIR = 0)
6048B–ATARM–29-Jun-06