AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 281

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 25-11. Overload Frame
25.4.3.5
6048B–ATARM–29-Jun-06
End of Frame
or Error Delimiter
or Overload Delimiter
Interframe Spacing
If a CAN node samples a dominant bit at the eighth bit (the last one) of an error delimiter or
overload delimiter, it starts transmitting an overload frame (not an error frame). The error
counters are incremented.
The start of an overload frame due to the first overload condition is only allowed to be started
at the first bit time of an expected intermission, whereas overload frames due to the second
overload condition and condition 3 start one bit after detecting the dominant bit.
At most two overload frames may be generated to delay the next data or remote frame.
Overload Flag
The overload flag consists of six dominant bits. The overall form corresponds to that of the
active error flag.
The overload flag’s form destroys the fixed form of the intermission field. As a consequence,
all other nodes also detect an overload condition and start transmission of an overload flag. If
there is a dominant bit detected during the 3rd bit of intermission, then it interpret this bit as
start of frame.
Note:
Overload Delimiter
The overload delimiter consists of eight recessive bits.
The overload delimiter is of the same form as the error delimiter. After transmission of an over-
load flag, the node monitors the bus until it detects a transition from a dominant to a recessive
bit. At this time, every bus node has finished sending its overload flag and all nodes start
transmission of seven more recessive bits simultaneously.
Data frames and remote frames are separated from preceding frames whatever type they are
(data frame, remote frame, error frame, overload frame) by a bit field called interframe space.
In contrast, overload frames and error frames are not preceded by an interframe space and
multiple overload frames are not separated by an interframe space.
Interframe Space
The interframe space contains the bit field intermission and bus idle and, for error passive
nodes that have been transmitter of the previous message, suspend transmission.
1. The internal conditions of a receiver, requiring a delay of the next data frame or
2. Detection of a dominant bit at the first and second bit of intermission.
Overload Flag
Superposition of Overload Flags
remote frame.
Controllers based on the CAN Specification version 1.0 and 1.1 have another interpretation of
the 3rd bit of intermission: if a dominant bit was detected locally at some node, the other nodes
do not interpret the overload flag correctly, but interpret the first of these six dominant bits as
start of frame; the sixth dominant bit violates the rule of bit stuffing causing an error condition.
Overload Frame
Overload
Delimiter
Interface Space
or Overload Frame
AT91SAM7A1
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