AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 335

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

26.11 General-purpose Timer in Capture Mode
26.11.1
26.11.1.1
6048B–ATARM–29-Jun-06
Description
Measure TIOA Pulse and Phase between TIOB and TIOA
The capture (wave measurement) mode is entered by setting WAVE (bit [15] in the Mode Reg-
ister) to 0.
It is the default operating mode after a hardware reset. It forces TIOAx and TIOBx pins as
input pins.
The capture mode provides the possibility to determine the duration between two events. An
event may either be an external input signal on TIOAx or TIOBx or an internal event (software
trigger or equality between the counter and a predefined compare value). An external event
(rising or falling edge) on TIOAx can result in capture register A being loaded, capture register
B being loaded or a trigger effect (reset and start the counter).
A predefined compare value (16-bit) can be set in the compare register C.
When the capture register B is loaded, it can disable the counter clock and/or stop the counter.
The user may choose an internal clock source (CORECLK/2, CORECLK/8, CORECLK/32,
CORECLK/128 or CORECLK/1024) or an external clock (TCLK0, TCLK1 or TCLK2).
A burst mode is available. It generates a burst clock. For more details, refer to
on page
Six interrupts can be produced:
Finally, the synchronize register can be used to cause a software trigger for reset and start the
counter at the next valid counter clock edge on all channels at the same time.
Figure 26-5
For more details, refer to application notes.
A TIOBx rising edge resets and starts the counter. A rising TIOAx edge loads RA and a falling
TIOAx edge loads RB. Once RB is loaded, a trigger restarts a capture cycle. RA contains the
phase between TIOBx and TIOAx. (RB - RA) is the duration of the TIOAx pulse.
• External trigger detected
• RA loaded
• RB loaded
• Counter overflow (when the counter passes from 0xFFFF to 0x0000)
• Overrun (when RA or RB is reloaded before the old value is read)
• Compare RC (the counter reaches the value stored in register C)
317.
to
Figure 26-8
show different applications using the capture mode.
AT91SAM7A1
”Clock Sources”
335