AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 319

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

26.4.1
26.5
26.5.1
6048B–ATARM–29-Jun-06
16-bit Registers
Counter Reset
Example
During counting, the counter can be reset to 0x0000 following:
Each time it is reset, the counter passes to 0x0000 at the next valid counter clock edge. See
Figure
Figure 26-4. Counter Reset Diagram
Each channel contains three 16-bit registers.
The mode determines whether the capture/compare registers are used as capture registers or
compare registers.
In capture mode, registers A and B are capture registers and can be loaded by TIOAx edges.
In waveform mode, registers A and B are compare registers.
Register C is always a compare register. The compare registers can generate a counter reset
(RC) or a waveform modification (RA, RB and RC) when the counter reaches the value pro-
grammed in them.
In an application, the required compare register values must be calculated using the following
equation:
where:
t = desired timer compare period (in seconds)
CLK = counter clock (in Hertz)
To determine the value needed in a compare register to obtain an equality with the counter
after 0.1 second with CORECLK = 30 MHz:
The value of the divider greater than or equal to 457.77 is DIV
• a software Trigger
• an external Trigger
• an equality on Compare C
• the synchronous bit TCSYNC of the block control register GPT_BCR.
1. Determine the minimal prescale value by dividing CORECLK by the maximal counter
value 0xFFFF (65,535) to know the divisor factor:
26-4.
CompareValue
30 000 000
----------------------------------- -
65 535
Clock
Counter
Counter
Trigger
=
=
457.77
xxxx
t
CLK
0x0000
–
1
0x0001
0x0002
min
= 1024.
AT91SAM7A1
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