AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 66

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.1.4
Name:
Access:
Address:
• PSTB[9:0]: PLL Stabilization Time
Number of clock cycles needed before PLL stabilization. This register must be configured by the software after a hardware
reset and before using the PLL.
The required time for PLL stabilization is T
The default value is 0x000000B0 guaranteeing 176 x 256 MCK clock cycles (i.e., 11.264 ms with MCK = 4.0 MHz).
When the clock manager is configured in LPM mode and the program enables both the PLL and the master oscillator,
PSTB should include the oscillator stabilization time and the PLL stabilization time. This is due to the fact that PSTB
counter and OSTB counter decrement in parallel.
The PLL transient behavior before mathematical locking (phase error between the reference signal and derived signal less
than ± 2 ) is complex and difficult to describe using simple mathematical expression. Thus, there is no general formula giv-
ing the set-up time for any step-response transient behavior that unlocks the loop. Nevertheless, this set-up time can be
approximated by a simple loop filter capacitor charging time T
where:
This formula overestimates the required time, but gives an easy way to approximate this setup time.
• PSTKEY[15:0]: Key for Write Access into the CM_PST Register
Any write in PSTB[9:0] are effective only if PSTKEY[15:0] is equal to 0x59C1. These bits are always read at 0.
Note:
66
– C3 and C4 are the loop filter capacitors,
– I
–
31
23
15
–
7
Write accesses to this register are only valid if PLLEN is at logical 0 (i.e., PLL not enabled).
p
is a margin factor, set to 3 or 4 as a minimum
the charge pump current (see
AT91SAM7A1
CM PLL Stabilization Timer Register
CM_PST
Read/Write
0xFFFEC00C
T
SETUP
30
22
14
–
6
C3
-------------------- -
I
+
P
C4
29
21
13
–
5
”PLL Characteristics” on page
VDDPLLV3
------------------------------- -
SETUP
2
minimum and is based on the MCK/256 clock (MCKEN = 1).
28
20
12
–
4
PSTKEY[15:8]
PSTKEY[7:0]
PSTB[7:0]
SETUP
in the worst case:
27
19
11
–
3
15),
26
18
10
–
2
25
17
9
1
PSTB[9:8]
6048B–ATARM–29-Jun-06
24
16
8
0