AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 248

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AT91SAM7A1-AU

Manufacturer Part Number
AT91SAM7A1-AU
Description
IC ARM7 MCU 32BIT ROMLESS144LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM7A1-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
49
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7A1-AU
Manufacturer:
Atmel
Quantity:
10 000
22.6.22
Name:
Access:
Address:
• RDRF: Receive Data Register Full Interrupt Mask
0: Receive Data Register Full Interrupt is disabled.
1: Receive Data Register Full Interrupt is enabled.
• TDRE: Transmit Data Register Empty Interrupt Mask
0: Transmit Data Register Empty Interrupt is disabled.
1: Transmit Data Register Empty Interrupt is enabled.
• MODF: Mode Fault Error Interrupt Mask
0: Mode Fault Interrupt is disabled.
1: Mode Fault Interrupt is enabled.
Only used in Master Mode.
• SPIOVRE: Overrun Error Interrupt Mask
0: Overrun Error Interrupt is disabled.
1: Overrun Error Interrupt is enabled.
• REND: PDC Reception End Interrupt Mask
0: Reception End Interrupt is disabled.
1: Reception End Interrupt is enabled.
• TEND: PDC Transfer End Interrupt Mask
0: Transfer End Interrupt is disabled.
1: Transfer End Interrupt is enabled.SPCK, MISO, MOSI, NPCS0, NPCS1, NPCS2, NPCS3: PIO Interrupt Mask
These bits show which pins have interrupts enabled. They are updated when interrupts are enabled or disabled by writing
to SPI_IER or SPI_IDR.
0: Interrupt is not enabled on the corresponding input pin.
1: Interrupts is enabled on the corresponding input pin.
248
31
23
15
7
AT91SAM7A1
SPI Interrupt Mask Register
SPI_IMR
Read-only
0xFFFB407C
NPCS3
30
22
14
6
NPCS2
TEND
29
21
13
5
NPCS1
REND
28
20
12
4
SPIOVRE
NPCS0
27
19
11
3
MODF
MOSI
26
18
10
2
TDRE
MISO
25
17
9
1
6048B–ATARM–29-Jun-06
RDRF
SPCK
24
16
8
0

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