LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 104

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LSI53C825AJ

Manufacturer Part Number
LSI53C825AJ
Description
Manufacturer
LSI
Datasheet

Specifications of LSI53C825AJ

Lead Free Status / RoHS Status
Not Compliant
4-16
R
DSI
APS
PMEC
VER[2:0]
Register: 0x44
Power Management Control/Status
Read Write
This register applies to the LSI53C825AE only and indicates the power
management control and status descriptions.
PST
DSCL
DSLT
Registers
PST DSCL
15
0
14 13 12
0
0
0
Reserved
Device Specific Initialization
This bit is cleared to indicate that the LSI53C825A
requires no special initialization before the generic class
device driver is able to use it.
Auxiliary Power Source
Because the device does not provide a PME signal, this
bit always returns a 0. This indicates that no auxiliary
power source is required to support the PME signal in the
D3cold power management state.
PME Clock
This bit always returns a zero value because the devices
do not provide a PME signal.
Version
This field is set of 001b to indicate that the device
complies with Revision 1.0 of the PCI Power
Management Interface Specification.
PME Status
The LSI53C825A always returns a zero for this bit,
indicating that PME signal generation is not supported
from D3cold.
Data Scale
The LSI53C825A does not support the
Therefore these two bits are always set to 00b.
Data Select
This device does not support the
these four bits are always set to 0000b.
0
DSLT
0
9
0
PEN
8
0
0
7
0
0
R
Data
0
register. Therefore
0
Data
2
0
register.
1
0
[14:13]
PWS
[12:9]
[8:6]
[2:0]
0
0
15
5
4
3

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