LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 111

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

TRG
Register: 0x01 (0x81)
SCSI Control One (SCNTL1)
Read/Write
EXC
ADB
Operating Registers
Caution:
EXC
7
0
ADB
6
0
Writing this bit while not connected may cause the loss of
a selection or reselection due to the changing of target or
initiator modes.
Target Mode
This bit determines the default operating mode of the
LSI53C825A. The user must manually set the target or
initiator mode. This is done using the SCRIPTS language
(SET TARGET or CLEAR TARGET). When this bit is set, the
chip is a target device by default. When this bit is cleared,
the LSI53C825A is an initiator device by default.
Extra Clock Cycle of Data Setup
When this bit is set, an extra clock period of data setup
is added to each SCSI data transfer. The extra data setup
time can provide additional system design margin, though
it affects the SCSI transfer rates. Clearing this bit disables
the extra clock cycle of data setup time. Setting this bit
only affects SCSI send operations.
Assert SCSI Data Bus
When this bit is set, the LSI53C825A drives the contents
of the
data bus. When the LSI53C825A is an initiator, the SCSI
I/O signal must be inactive to assert the SODL contents
onto the SCSI bus. When the LSI53C825A is a target, the
SCSI I/O signal must be active to assert the SODL
contents onto the SCSI bus. The contents of the
Output Data Latch (SODL)
any time, even before the LSI53C825A is connected to
the SCSI bus. Clear this bit when executing SCSI
SCRIPTS. It is normally used only for diagnostic testing
or operation in low level mode.
DHP
SCSI Output Data Latch (SODL)
5
0
CON
4
0
RST
3
0
register can be asserted at
AESP
2
0
onto the SCSI
IARB
1
0
SCSI
SST
0
0
4-23
0
7
6