LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 85

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

3.1.9 JTAG Signals
Table 3.10
3.2 MAD Bus Programming
Name
TCK
TMS
TDI
TDO
JTAG Signals (LSI53C825AJ, LSI53C825AJE Only)
Pin No.
130/130
142/142
57/57
58/58
Table 3.10
The MAD[7:0] pins, in addition to serving as the address/data bus for the
local memory interface, are also used to program power-up options for
the chip. A particular option is programmed by connecting a 4.7 k
resistor between the appropriate MAD(x) pin and Vss. The pull-down
resistors require that HC or HCT external components are used for a
memory interface.
MAD Bus Programming
MAD[7] – has no functionality. Do not place a pull-down resistor on
this pin.
MAD[6] – Subsystem Data configuration. Please refer to the
Table 3.11
MAD[5] – SCRIPTS RAM disable. Connecting a 4.7 k
between MAD[5] and Vss disables SCRIPTS RAM.
MAD[4] – Subsystem Data configuration. Please refer to the
Table 3.11
Type
describes the signals for the JTAG Signals group:
–
–
–
–
for the different configurations.
and
Description
Test Clock pin for JTAG boundary scan.
Test Mode Select pin for JTAG boundary scan.
Test Data In pin for JTAG boundary scan.
Test Data Out pin for JTAG boundary scan.
Table 3.12
below for the different configurations.
resistor
3-15