LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 114

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-26
Register: 0x02 (0x82)
SCSI Control Two (SCNTL2)
Read/Write
SDU
CHM
Registers
Caution:
SDU
7
0
CHM
6
0
Writing to this register while not connected may cause the
loss of a selection/reselection by clearing the Connected
bit.
SCSI Disconnect Unexpected
This bit is valid in the initiator mode only. When this bit is
set, the SCSI core is not expecting the SCSI bus to enter
the Bus Free phase. If it does, an unexpected disconnect
error is generated (see the Unexpected Disconnect bit in
the
During normal SCRIPTS mode operation, this bit is set
automatically whenever the SCSI core is reselected, or
successfully selects another SCSI device. The SDU bit
should be cleared with a register write (Move 0x00 To
SCSI Control Two
expects a disconnect to occur, normally prior to sending
an Abort, Abort Tag, Bus Device Reset, Clear Queue or
Release Recovery message, or before deasserting
SACK/ after receiving a Disconnect command or
Command Complete message.
Chained Mode
This bit determines whether or not the SCSI core is
programmed for chained SCSI mode. This bit is
automatically set by the Chained Block Move (CHMOV)
SCRIPTS instruction and is automatically cleared by the
Block Move SCRIPTS instruction (MOVE).
Chained mode is primarily used to transfer consecutive
wide data blocks. Using chained mode facilitates partial
receive transfers and allows correct partial send behavior.
When this bit is set and a data transfer ends on an odd
byte boundary, the LSI53C825A stores the last byte in
the
receive operation, or in the
SCSI Interrupt Status Zero (SIST0)
SCSI Wide Residue (SWIDE)
SLPMD SLPHBEN
5
0
4
0
(SCNTL2)) before the SCSI core
WSS
3
0
SCSI Output Data Latch
VUE0
2
0
register during a
register, bit 2).
VUE1
1
0
WSR
0
0
7
6