LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 82

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Table 3.8
3-12
Name
GPIO1_
MASTER/
GPIO[4:3]
DIFFSENS
MAC/_
TESTOUT (Not
available on
LSI53C825AJ)
IRQ/
Additional Interface Signals (Cont.)
Pin No.
58, NA
71, 70
52/69/
M5
Signal Descriptions
54
72
Type Description
T/S
I/O
I/O
O
I
General purpose I/O pin. Optionally, when driven LOW,
indicates that the LSI53C825A is bus master. This pin powers
up as a general purpose input.
LSI Logic SDMS software supports use of this signal in serial
EEPROM applications, when enabled, in combination with the
GPIO0 pin. When this signal is used as a clock for serial
EEPROM access, the GPIO1 pin serves as data, and the pin is
controlled from PCI configuration register 0x35.
General purpose I/O pins. GPIO4 powers up as an output. It
can be used as the enable line for V
to the external flash memory interface. GPIO3 powers up as an
input.
LSI Logic SDMS software uses GPIO3 to detect a differential
board. If the pin is pulled LOW externally, the board will be
configured by SDMS software as a differential board. If it is
pulled HIGH or left floating, SDMS software will configure it as
a SE board. The LSI Logic PCI to SCSI host adapters use the
GPIO4 pin in the process of flashing a new SDMS software
ROM.
The Differential Sense pin detects the presence of a SE device
on a differential system. When external differential transceivers
are used and a zero is detected on this pin, all chip SCSI
outputs will be 3-stated to avoid damage to the transceivers.
This pin should be tied HIGH during SE operation. The normal
value of this pin is 1.
Memory Access Control. This pin can be programmed to
indicate local or system memory accesses (non-PCI
applications). It is also used to test the connectivity of the
LSI53C825A signals using an “AND tree” scheme. The
MAC/_TESTOUT pin is only driven as the Test Out function
when the TESTIN/ pin is driven LOW.
Interrupt. This signal, when asserted LOW, indicates that an
interrupting condition has occurred and that service is required
from the host CPU. The output drive of this pin is programmed
as either open drain with an internal weak pull-up or, optionally,
as a totem pole driver. Refer to the description of
(DCNTL)
register, bit 3, for additional information.
PP
, the 12 Volt power supply
DMA Control