LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 155

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

ERL
ERMP
BOF
MAN
Operating Registers
Enable Read Line
This bit enables a PCI Read Line command. If the PCI
cache mode is enabled by setting bits in the PCI
Line Size
on all read cycles if other conditions are met. For more
information on these conditions, refer to
nal Descriptions.”
Enable Read Multiple
This bit, when set, causes Read Multiple commands to
be issued on the PCI bus after certain conditions have
been met. These conditions are described in
“Signal Descriptions.”
Burst Opcode Fetch Enable
Setting this bit causes the LSI53C825A to fetch
instructions in burst mode. Specifically, the chip bursts in
the first two Dwords of all instructions using a single bus
ownership. If the instruction is a memory-to-memory
move type, the third Dword is accessed in a subsequent
bus ownership. If the instruction is an indirect type, the
additional Dword is accessed in a subsequent bus
ownership. If the instruction is a table indirect block move
type, the chip accesses the remaining two Dwords in a
subsequent bus ownership, thereby fetching the four
Dwords required in two bursts of two Dwords each. This
bit has no effect if SCRIPTS instruction prefetching is
enabled.
Manual Start Mode
Setting this bit prevents the LSI53C825A from
automatically fetching and executing SCSI SCRIPTS
when the
written. When this bit is set, the Start DMA bit in the
Control (DCNTL)
execution. Clearing this bit causes the LSI53C825A to
automatically begin fetching and executing SCSI
SCRIPTS when the
register is written. This bit normally is not used for SCSI
SCRIPTS operations.
register, this chip issues a Read Line command
DMA SCRIPTS Pointer (DSP)
register must be set to begin SCRIPTS
DMA SCRIPTS Pointer (DSP)
Chapter 3, “Sig-
register is
Chapter 3,
Cache
DMA
4-67
3
2
1
0