LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 19

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

1.4.2 PCI Performance
To improve PCI performance, the LSI53C825A:
LSI53C825A Benefits Summary
Reduces ISR overhead through a unique interrupt status reporting
method
Performs fast and wide SCSI bus transfers in SE and differential
mode
–
20 Mbytes/s synchronous Load/Store SCRIPTS instruction increases
performance of data transfers to and from chip registers
Supports target disconnect and later reconnect with no interrupt to
the system processor
Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast
I/O context switching
Expanded Register Move instruction supports additional arithmetic
capability
Complies with PCI Bus Power Management Specification
(LSI53C825AE), Revision 1.0
Complies with PCI 2.1 specification
Bursts 2, 4, 8, 16, 32, 64, or 128 Dwords across PCI bus
Supports 32-bit word data bursts with variable burst lengths
Prefetches up to 8 Dwords of SCRIPTS instructions
Bursts SCRIPTS opcode fetches across the PCI bus
Performs zero wait-state bus master data bursts faster than
110 Mbytes/s (@ 33 MHz)
Supports PCI
Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands
10 Mbytes/s asynchronous
Cache Line Size
register
1-5