LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 178

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-90
SZM
AWS
EXT
LOW
Registers
Note:
Note:
Never set this bit during Fast SCSI (greater than 5 Mbytes
transfers per second) operations, because a valid assertion
could be treated as a glitch.
It is not necessary to set this bit for access to the SCSI
bit-level registers
Bus Control Lines
SCSI High Impedance Mode
Setting this bit places all the open drain 48 mA SCSI
drivers into a high impedance state. This is to allow
internal loopback mode operation without affecting the
SCSI bus.
Always Wide SCSI
When this bit is set, all SCSI information transfers are
done in the 16-bit wide mode. This includes data,
message, command, status, and reserved phases.
Normally, deassert this bit since 16-bit wide message,
command, and status phases are not supported by the
SCSI specifications.
Extend SREQ/SACK/ Filtering
LSI Logic TolerANT SCSI receiver technology includes a
special digital filter on the SREQ/ and SACK/ pins which
causes the disregarding of glitches on deasserting
edges. Setting this bit increases the filtering period from
30 ns to 60 ns on the deasserting edge of the SREQ/ and
SACK/ signals.
SCSI Low level Mode
Setting this bit places the LSI53C825A in low level mode.
In this mode, no DMA operations occur, and no SCRIPTS
execute. Arbitration and selection may be performed by
setting the start sequence bit as described in the
Control Zero (SCNTL0)
performed by manually asserting and polling SCSI
signals. Clearing this bit allows instructions to be
executed in the SCSI SCRIPTS mode.
(SCSI Output Data Latch
(SBCL), and input registers).
register. SCSI bus transfers are
(SODL),
SCSI
SCSI
3
2
1
0