LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 59

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Figure 2.5
2.4.13 Interrupt Handling
2.4.13.1 Polling and Hardware Interrupts
CCF2
SCLK
0
0
0
1
0
CCF1
0
1
1
0
0
SCF2
0
0
0
1
0
Determining the Synchronous Transfer Rate
CCF0
1
0
1
0
0
SCF1
The SCRIPTS processor in the LSI53C825A performs most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C825A.
The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit set that
indicates an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of
PCI Cache Mode
0
1
1
0
0
Divisor
1.5
1
2
3
3
SCF0
1
0
1
0
0
Divisor
SCF
1.5
1
2
3
3
Divider
Divider
SCF
CCF
This point
must not
50 MHz
exceed
Example:
SCLK = 40 MHz, SCF = 1, XFERP = 4,
SCSI transfer rate = 10 MHz, CCF = 2
(40 MHz
(40 MHz
10 Mbytes/s on an 8-bit SCSI bus)
This point
must not
25 MHz
exceed
TP2
0
0
0
0
1
1
1
1
1 = synchronous core rate)
4 = 10 MHz synchronous rate =
Asynchronous
Divide by 4
Synchronous
SCSI Logic
Divider
TP1
0
0
1
1
0
0
1
1
TP0
0
1
0
1
0
1
0
1
(to SCSI Bus)
Send Clock
Receive
Clock
XFERP
Divisor
4
5
6
7
8
9
10
11
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