LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 143

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

CLF
FM
WRIE
Operating Registers
Note:
Note:
Polling of FIFO flags is allowed during flush operations.
This bit does not clear the data visible at the bottom of the
FIFO.
Next Address (DNAD)
signal, controlled by the
register, determines the direction of the transfer. This bit
is not self-clearing; clear it once the data is successfully
transferred by the LSI53C825A.
Clear DMA FIFO
When this bit is set, all data pointers for the DMA FIFO
are cleared. Any data in the FIFO is lost. After the
LSI53C825A successfully clears the appropriate FIFO
pointers and registers, this bit automatically clears.
Fetch Pin Mode
When set, this bit causes the FETCH/ pin to deassert
during indirect and table indirect read operations.
FETCH/ is only active during the opcode portion of an
instruction fetch. This allows the storage of SCRIPTS in
a PROM while data tables are stored in RAM.
If this bit is not set, FETCH/ is asserted for all bus cycles
during instruction fetches.
Write and Invalidate Enable
This bit, when set, causes the issuing of Write and
Invalidate commands on the PCI bus whenever legal.
The Write and Invalidate Enable bit in the PCI
Configuration
order for the chip to generate Write and Invalidate
commands.
Command
register. The internal DMAWR
Chip Test Five (CTEST5)
register must also be set in
4-55
2
1
0