LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 294

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

DMA (Cont.)
DMA core
DSA
DSPS register
E
enable
encoded
error reporting signals
expansion ROM base address
extend SREQ/SACK filtering (EXT)
external
external memory interface
extra clock cycle of data setup (EXC)
F
fetch
FIFO
first dword
flush DMA FIFO (FLF)
full arbitration, selection/reselection
function complete
G
general purpose
IX-4
interrupt pending (DIP)
mode (DMODE)
next address (DNAD)
SCRIPTS
status (DSTAT)
relative
parity
read
response to
wide SCSI (EWS)
chip SCSI ID (ENC[3:0])
destination SCSI ID
SCSI destination ID
clock
configuration
flash ROM updates
memory sizes supported
multiple byte accesses
slow memory
system requirements
enable (FE)
pin mode (FM)
byte control (FBL[2:0])
flags (FF[3:0])
flags, bit 4 (FF4)
(CMP)
(GPREG)
I/O (GPIO[4:0])
pointer (DSP)
pointer save (DSPS)
checking (EPC)
line (ERL)
multiple (ERMP)
reselection (RRE)
selection (SRE)
(ENC[3:0])
(ENID[3:0])
6-11
2-11
4-71
5-6
5-41
4-35
,
5-38
,
4-80
5-14
2-16
4-74
2-16
4-66
4-44
4-35
4-55
4-39
4-35
4-40
4-64
,
4-47
4-63
4-29
3-9
5-24
4-54
4-22
4-30
2-14
5-22
4-66
2-14
4-62
4-30
2-14
4-58
6-13
,
4-51
Index
4-63
4-30
2-16
5-29
4-11
,
4-89
5-41
4-21
4-23
GPIO enable (GPIO[1:0])
GPIO enable (GPIO[4:2])
H
halt SCSI clock (HSC)
handshake-to-handshake
header type (HT[7:0])
high impedance mode (SZM)
high impedance mode (ZMOD)
HVD or SE/LVD (DIF)
I
I/O
illegal instruction detected (IID)
immediate
indirect addressing
initiator
input
instruction
instructions
INTA, INTB disable (IRQD)
interface control signals
interrupt
interrupt-on-the-fly instruction
interrupts
IRQ mode (IRQM)
J
jump
pin control (GPCNTL)
timer expired (GEN)
timer period (GEN[3:0])
timer scale factor (GENSF)
timer bus activity enable (HTHBA)
timer expired (HTH)
timer period (HTH[3:0])
timer scale factor (HTHSF)
instructions
arbitration (IARB)
data
mode
type
block move
instruction
line
on the fly
on-the-fly (INTF)
output
pin (IP[7:0])
status (ISTAT)
fatal vs. nonfatal interrupts
halting
masking
sample interrupt service routine
stacked interrupts
address
3-4
phase mismatch
block move
I/O instruction
memory move
read/write instruction
transfer control instruction
4-13
5-26
5-41
2-35
5-18
6-13
2-40
5-36
2-38
5-35
5-32
5-14
5-6
4-13
4-48
4-69
5-6
5-6
4-50
4-25
4-9
5-14
2-39
5-37
4-88
4-90
4-73
3-8
4-73
4-74
4-80
4-80
4-80
4-81
4-84
4-69
,
5-24
,
5-33
4-89
4-76
4-76
2-37
4-84
4-83
4-57
4-41
5-29
2-41
,
4-67
4-83