LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 30

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.1.3.4 Memory Move Misalignment
2.1.3.5 Memory Write and Invalidate Command
2-6
Example: Cache Line Size - 16, Current Address = 0x01 – The chip
is not aligned to a 4 Dword cache boundary (the stepping threshold), so
it issues four single Dword transfers (the first is a 3-byte transfer). At
address 0x10, the chip is aligned to a 4 Dword boundary, but not aligned
to any higher burst size boundaries that are less than the cache line size.
So, the part issues a burst of 4. At this point, the address is 0x20, and
the chip evaluates that it is aligned not only to a 4 Dword boundary, but
also to an 8 Dword boundary. It selects the highest, 8, and burst
8 Dwords. At this point, the address is 0x40, which is a cache line size
boundary. Alignment stops, and the burst size from then on is switched
to 16.
The LSI53C825A does not operate in a cache alignment mode when a
Memory Move instruction type is issued and the read and write
addresses are different distances from the nearest cache line boundary.
For example, if the read address is 0x21F and the write address is 0x42F,
and the cache line size is 8, the addresses are byte aligned, but they are
not the same distance from the nearest cache boundary. The read
address is 1 byte from the cache boundary 0x220 and the write address
is 17 bytes from the cache boundary 0x440. In this situation, the chip
does not align to cache boundaries and operates as a LSI53C825.
The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line; that is to say, the master intends to
write all bytes within the addressed cache line in a single PCI transaction
unless interrupted by the target. This command requires implementation
of the PCI
space. The LSI53C825A enables Memory Write and Invalidate cycles
when bit 0 in the
the PCI
met, Memory Write and Invalidate commands are issued:
Functional Description
The CLSE bit, WRIE bit, and PCI configuration
bit 4 are set.
Command
Cache Line Size
Chip Test Three (CTEST3)
register are set. When the following conditions are
register at address 0x0C in PCI configuration
register (WRIE) and bit 4 in
Command
register,