LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 192

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Figure 5.2
5-8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 - Instruction Type - Block Move
DCMD Register
0 - Instruction Type - Block Move
Indirect Addressing (LSI53C700 Family Compatible)
Table Indirect Addressing
Block Move Instruction Register
Opcode
MSG/
SCSI SCRIPTS Instruction Set
C/D
I/O
Prior to the start of an I/O, the
(DSA)
the I/O data structure. The address may be any address
on a longword boundary.
After a Table Indirect opcode is fetched, the DSA is
added to the 24-bit signed offset value from the opcode
to generate the address of the required data; both
positive and negative offsets are allowed. A subsequent
fetch from that address brings the data values into the
chip.
For a MOVE instruction, the 24-bit byte count is fetched
from system memory. Then the 32-bit physical address is
brought into the LSI53C825A. Execution of the move
begins at this point.
DSPS Register
register should be loaded with the base address of
24-bit Block Move Byte Counter
DBC Register
Data Structure Address