LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 297

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

synchronous
synchronous data transfer rates
T
table indirect
table relative
target
target asynchronous receive
target asynchronous send
TEMP register
temporary (TEMP)
termination
third dword
timer test mode (TTM)
TolerANT
TolerANT technology
totem pole output
transfer
transfer rate
U
unexpected disconnect (UDC)
use data8/SFBR
V
vendor
W
wait
wide SCSI
won arbitration (WOA)
write
write and invalidate
clock conversion factor (SCF[2:0])
mode
mode
mode (TRG)
timing
enable (TE)
technology
benefits
control instructions
count
counter
synchronous
unique enhancement, bit 1 (VUE1)
unique enhancements, bit 0 (VUE0)
disconnect instruction
for valid phase
reselect instruction
select instruction
chained block moves
receive (WSR)
send (WSS)
read instructions
read system memory from SCRIPTS
enable (WRIE)
SATN/ active (M/A)
electrical characteristics
5-38
5-20
5-9
6-7
6-15
2-29
5-38
5-12
1-4
,
5-21
5-21
5-38
5-15
4-90
4-27
4-23
2-33
5-26
3-4
4-55
4-28
5-36
4-55
5-24
5-16
1-3
4-44
4-91
5-29
5-19
2-42
5-18
6-47
4-74
Index
6-48
4-72
6-7
2-33
,
4-75
4-28
4-27
4-27
5-38
IX-7