LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 138

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-50
CON
INTF
SIP
Registers
Note:
If the INTF bit is set but SIP or DIP is not set, do not
attempt to read the other chip status registers. An
interrupt-on-the-fly must be cleared before servicing any
other interrupts indicated by SIP or DIP.
This bit must be written to one in order to clear it after it
has been set.
notify an external processor of a predefined condition
while SCRIPTS are running. The external processor may
also notify the LSI53C825A of a predefined condition and
the SCRIPTS processor may take action while SCRIPTS
are executing.
Connected
This bit is automatically set any time the LSI53C825A is
connected to the SCSI bus as an initiator or as a target.
It is set after successfully completing selection or when
the LSI53C825A responds to a bus-initiated selection or
reselection. It is also set after the SCSI function wins
arbitration when operating in low level mode. When this
bit is cleared, the LSI53C825A is not connected to the
SCSI bus.
Interrupt-on-the-Fly
This bit is asserted by an INTFLY instruction during
SCRIPTS execution. SCRIPTS programs do not halt
when the interrupt occurs. This bit can be used to notify
a service routine, running on the main processor while
the SCRIPTS processor is still executing a SCRIPTS
program. If this bit is set, when the
(ISTAT)
clear this bit, write it to a one. The reset operation is
self-clearing.
SCSI Interrupt Pending
This status bit is set when an interrupt condition is
detected in the SCSI portion of the LSI53C825A. The
following conditions cause a SCSI interrupt to occur:
A phase mismatch (initiator mode) or SATN/ becomes
active (target mode)
An arbitration sequence completes
A selection or reselection time-out occurs
register is read it is not automatically cleared. To
Interrupt Status
3
2
1