LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 50

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2-26
Step 2. Read bit 7 in the
Step 3. If any wide transfers have been performed using the Chained
Synchronous SCSI Receive –
Step 1. If the DMA FIFO size is set to 88 bytes, subtract the seven least
Step 2. Read bits [7:4] of the
Step 3. If any wide transfers have been performed using the Chained
Functional Description
bits [1:0] in the
of the DMA FIFO register. AND the result with 0x3FF for a byte
count between zero and 536.
Two (SSTAT2)
SCSI Input Data Latch (SIDL)
Status Zero (SSTAT0)
least significant byte or the most significant byte is full,
respectively.
Move instruction, read the Wide SCSI Receive bit
Control Two
in the
significant bits of the
the 7-bit value of the
result with 0x7F for a byte count between zero and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the
Test Five (CTEST5)
bits of the
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the
of the
for a byte count between zero and 536.
bit 4 of the
representation of the number of valid bytes in the SCSI FIFO,
to determine if any bytes are left in the SCSI FIFO.
Move instruction, read the Wide SCSI Receive bit
Control Two
in the
Figure 2.2
each of the different modes.
SCSI Wide Residue (SWIDE)
DMA FIFO (DFIFO)
SCSI Wide Residue (SWIDE)
DMA Byte Counter (DBC)
shows how data is moved to/from the SCSI bus in
SCSI Status Two (SSTAT2)
(SCNTL2), bit 0) to determine whether a byte is left
(SCNTL2), bit 0) to determine whether a byte is left
register to determine if any bytes are left in the
Chip Test Five (CTEST5)
Chip Test Five (CTEST5)
SCSI Status Zero (SSTAT0)
register), subtract the 10 least significant
DMA Byte Counter (DBC)
DMA FIFO (DFIFO)
SCSI Status One (SSTAT1)
or
SCSI Status Two
register. AND the result with 0x3FF
register. If bit 7 is set in the
register.
register.
register from the 10-bit
register, the binary
register and bits [7:0]
register and bits [7:0]
register. AND the
(SSTAT2), then the
and
register from
SCSI Status
register and
(SCSI
(SCSI
SCSI
Chip