LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 134

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-46
Register: 0x0F (0x8F)
SCSI Status Two (SSTAT2)
Read Only
ILF1
ORF1
OLF1
Registers
ILF
7
0
ORF1
6
0
initiator or target mode. These bits are set when the
corresponding signal is active. They are useful when
operating in the low level mode.
SIDL Most Significant Byte Full
This bit is set when the most significant byte in the
Input Data Latch (SIDL)
from the SCSI bus to the
register before being sent to the DMA FIFO and then to
the host bus. The
contains SCSI data received asynchronously.
Synchronous data received does not flow through this
register.
SODR Most Significant Byte Full
This bit is set when the most significant byte in the SCSI
Output Data register (SODR, a hidden buffer register
which is not accessible) contains data. The SODR
register is used by the SCSI logic as a second storage
register when sending data synchronously. It is not
accessible to the user. This bit is used to determine how
many bytes reside in the chip when an error occurs.
SODL Most Significant Byte Full
This bit is set when the most significant byte in the
Output Data Latch (SODL)
put Data Latch (SODL)
the DMA logic and the SCSI bus. In synchronous mode,
data is transferred from the host bus to the
Data Latch (SODL)
Data register (SODR, a hidden buffer register which is
not accessible) before being sent to the SCSI bus. In
asynchronous mode, data is transferred from the host
bus to the
then to the SCSI bus. The SODR buffer register is not
OLF1
5
0
SCSI Output Data Latch (SODL)
FF4
4
0
SCSI Input Data Latch (SIDL)
register, and then to the SCSI Output
SPL1
contains data. Data is transferred
register is the interface between
3
0
SCSI Input Data Latch (SIDL)
contains data. The
DIFF
2
0
LDSC
1
0
SCSI Output
register, and
SCSI Out-
register
SDP1
SCSI
SCSI
0
0
7
6
5