LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 154

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-66
SIOM
DIOM
Registers
1. Only valid if the FIFO size is set to 536 bytes.
transfers is performed. The LSI53C825A inserts a
“fairness delay” of four CLKs between burst transfers (as
set in BL[1:0]) during normal operation. The fairness
delay is not inserted during PCI retry cycles. This gives
the CPU and other bus master devices the opportunity to
access the PCI bus between bursts.
Source I/O-Memory Enable
This bit is defined as an I/O Memory Enable bit for the
source address of a Memory Move or Block Move
Command. If this bit is set, then the source address is in
I/O space; and if cleared, then the source address is in
memory space.
This function is useful for register-to-memory operations
using the Memory Move instruction when a LSI53C825A
is I/O mapped. Bits 4 and 5 of the
(CTEST2)
configuration status of the LSI53C825A.
Destination I/O-Memory Enable
This bit is defined as an I/O Memory Enable bit for the
destination address of a Memory Move or Block Move
Command. If this bit is set, then the destination address
is in I/O space; and if cleared, then the destination
address is in memory space.
This function is useful for memory-to-register operations
using the Memory Move instruction when a LSI53C825A
is I/O mapped. Bits 4 and 5 of the
(CTEST2)
configuration status of the LSI53C825A.
(CTEST5 bit 2)
BL2
0
0
0
0
1
1
1
1
register are used to determine the
register are used to determine the
BL1
0
0
1
1
0
0
1
1
BL0
0
1
0
1
0
1
0
1
Chip Test Two
Chip Test Two
128-transfer burst
32-transfer burst
64-transfer burst
16-transfer burst
2-transfer burst
4-transfer burst
8-transfer burst
Burst Length
Reserved
1
1
1
5
4