LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 177

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x4E (0xCE)
SCSI Test Two (STEST2)
Read/Write
SCE
ROF
DIF
SLB
Operating Registers
SCE
7
0
Note:
ROF
6
0
Do not set this bit during normal operation, since it could
cause contention on the SCSI bus. It is included for
diagnostic purposes only.
SCSI Control Enable
Setting this bit allows assertion of all SCSI control and
data lines through the
and
of whether the LSI53C825A is configured as a target or
initiator.
Reset SCSI Offset
Setting this bit clears any outstanding synchronous
SREQ/SACK offset. If a SCSI gross error occurs, set this
bit. This bit automatically clears itself after resetting the
synchronous offset.
SCSI Differential Mode
Setting this bit allows the LSI53C825A to interface
properly to external differential transceivers. Its only real
effect is to 3-state the SBSY/, SSEL/, and SRST/ pads so
that they can be used as pure inputs. Clearing this bit
enables SE mode operation. This bit should be set in the
initialization routine if the differential pair interface is
used.
SCSI Loopback Mode
Setting this bit allows the LSI53C825A to perform SCSI
loopback diagnostics. That is, it enables the SCSI core to
simultaneously perform as both the initiator and the
target.
SCSI Output Data Latch (SODL)
DIF
5
0
SLB
4
0
SCSI Output Control Latch (SOCL)
SZM
3
0
AWS
2
0
registers regardless
EXT
1
0
LOW
0
0
4-89
7
6
5
4